Programmable Memristive Threshold Logic Gate Array

dc.contributor.author	Olga Krestinskaya; Akshay Kumar Maan; Alex Pappachen James
dc.date.accessioned	2025-08-06T09:13:52Z
dc.date.available	2025-08-06T09:13:52Z
dc.date.issued	2018
dc.description.abstract	This paper proposes the implementation of a programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high‑speed processing and computation. Unlike existing architectures, the proposed TLG array operation does not depend on input signal timing or pulses. The circuit is implemented using TSMC 180 nm CMOS technology. In simulations of a 3 × 4 TLG array, the on‑chip area is 1463 μm² and power dissipation is 425 μW.
dc.identifier.citation	Krestinskaya, O.; Maan, A. K.; James, A. P. (2018). Programmable Memristive Threshold Logic Gate Array. In 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2018), Chengdu, China, Oct 26–30, pp. 313–316. IEEE. DOI: 10.1109/APCCAS.2018.8605646
dc.identifier.uri	https://nur.nu.edu.kz/handle/123456789/9063
dc.language.iso	en
dc.subject	programmable threshold logic gate
dc.subject	memristive TLG crossbar array
dc.subject	modified TLG cells
dc.subject	CMOS 180 nm
dc.subject	on-chip area
dc.subject	power dissipation
dc.subject	high-speed computation
dc.title	Programmable Memristive Threshold Logic Gate Array
dc.type	Article

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