Programmable Memristive Threshold Logic Gate Array

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dc.contributor.authorKrestinskaya, Olga
dc.contributor.authorMaan, Akshay Kumar
dc.contributor.authorJames, Alex Pappachen
dc.contributor.institutionDepartment of Electrical and Computer Engineering, Nazarbayev University
dc.date.accessioned2025-08-06T09:13:52Z
dc.date.available2025-08-06T09:13:52Z
dc.date.issued2018
dc.description.abstractThis paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm2 and 425μW, respectively.
dc.identifier.citationKrestinskaya, O., Maan, A. K., & James, A. P. (2018, October). Programmable memristive threshold logic gate array. In 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 313-316). IEEE. doi: 10.1109/APCCAS.2018.8605646.
dc.identifier.doi10.1109/APCCAS.2018.8605646.
dc.identifier.urihttps://doi.org/10.1109/APCCAS.2018.8605646.
dc.identifier.urihttps://nur.nu.edu.kz/handle/123456789/9063
dc.language.isoen
dc.publisherIEEE
dc.rightsAll Rights Reserved
dc.source2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 313-316)
dc.subjectProgrammable threshold logic gate
dc.subjectMemristive TLG crossbar array
dc.subjectModified TLG cells
dc.subjectCMOS 180 nm
dc.subjectOn-chip area
dc.subjectPower dissipation
dc.subjectHigh-speed computation
dc.titleProgrammable Memristive Threshold Logic Gate Array
dc.typeConference paper

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