Programmable Memristive Threshold Logic Gate Array

Abstract

This paper proposes the implementation of a programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high‑speed processing and computation. Unlike existing architectures, the proposed TLG array operation does not depend on input signal timing or pulses. The circuit is implemented using TSMC 180 nm CMOS technology. In simulations of a 3 × 4 TLG array, the on‑chip area is 1463 μm² and power dissipation is 425 μW.