30 Gb/s integrated receiver array for parallel optical interconnects
| dc.contributor.author | Nguyen, Nga T. H. | |
| dc.contributor.author | Ukaegbu, Ikechi | |
| dc.contributor.author | Park, Hyo-Hoon | |
| dc.date.accessioned | 2019-12-18T06:27:52Z | |
| dc.date.available | 2019-12-18T06:27:52Z | |
| dc.date.issued | 2019-08 | |
| dc.description.abstract | A 30 Gb/s integrated receiver array for parallel optical interconnects with four channels have been designed and implemented in a 0.13 mu m CMOS technology. To achieve small area and low power consumption while maintaining large bandwidth and high gain, the integrated receiver has been implemented with a regulated cascode (RGC) transimpedance amplifier (TIA), resistive and capacitive degeneration and inductorless limiting amplifier (LA), which employs active feedback and negative capacitance. From the measurement results of the optical module using 850 nm photodiode (PD), the receiver showed a constant single-ended output swing of 320 mV up to 7.5 Gb/s/ch with clear eye diagrams and BER of <10(-12). With a voltage supply of 1.2 V, a figure of merit (FOM) of 8 mW/Gb/s was obtained with a small chip area per channel of 0.28 mm(2)/ch. | en_US |
| dc.identifier.citation | Nguyen, N. T., Ukaegbu, I. A., & Park, H. H. (2019). 30 Gb/s integrated receiver array for parallel optical interconnects. The Journal of Engineering, 2019(8), 5375-5378. | en_US |
| dc.identifier.uri | http://nur.nu.edu.kz/handle/123456789/4469 | |
| dc.language.iso | en | en_US |
| dc.publisher | IET | en_US |
| dc.rights | Attribution-NonCommercial-ShareAlike 3.0 United States | * |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/3.0/us/ | * |
| dc.title | 30 Gb/s integrated receiver array for parallel optical interconnects | en_US |
| dc.type | Article | en_US |
| workflow.import.source | science |