Memristor-Based Multilevel Memory Circuit for Hierarchical Temporal Memory

Abstract

Ideally, a memristor has infinite memory states making it a promising device as an analog memory. However, real memristors are limited by the number of states and non-idealities make it even more challenging to retain and program a large set of stable states. In this thesis, we propose a multilevel memory cell design consisting of two memristors, one resistor and one transistor for discrete level storage and computing. By using different combinations of ON and OFF memristor, binary, ternary, and quaternary memory states are implemented. The design simplifies the writing and reading processes and makes the overall circuitry more reliable relative to the existing designs. Tanner software simulations indicate that the cell is robust to variabilities and show distinctive output voltages so that each memory state can be reliably differentiated. Such multilevel memory cell is essential for building intelligent machines. Hence, the proposed memory cell is applied for Hierarchical Temporal Memory (HTM) machine learning algorithm which replicates the structure of the human neocortex. In particular, we propose to use the memory cell for HTM Temporal Memory (TM) part for storing so called class-map which is a reference image representing a particular class. It is created based on important and unimportant features of training images within a class. With this technique there is no need to store all training images as a result of which memory requirements are reduced. For HTM Spatial Pooler (SP) which is necessary for generating Sparse Distributed Representations (SDRs) and pattern matching needed for classification, we adopted algorithms with existing hardware architectures. The software algorithm of the proposed methodology of HTM implementation was developed and tested with Yale face image dataset in Matlab. The maximum accuracy of Monte-Carlo simulations with model selection is achieved to be 83.37%.