DESIGN OF A CONVOLUTION OPERATION ACCELERATOR FOR CNNS USING AN FPGA

Abstract

Training convolutional neural networks (CNNs) demands significant computational resources and specialized hardware. Custom accelerators have emerged as an efficient alternative to traditional graphics processing units (GPUs), offering higher throughput, and decreased physical footprint at low costs. In this paper, we present a bit-serial multiplier based architecture for convolution acceleration. This design offers a hardware accelerator in a DE1-SoC board that utilizes an FPGA and ARM processor on the board. The main processing unit in the design is a novel bit-serial multiplier architecture that minimizes the hardware usage and overall area on the board.