LLM-DRIVEN MUTATION TESTING IN MICROARCHITECTURE VERIFICATION

Abstract

The majority of electronic devices people use daily operate with microarchitectures at their core. As manufacturers release new iterations of these devices, microarchitecture scale and complexity continuously increase. This results in the rise of verification complexity. The costs of poor verification are extremely high. Lost funds, chip respins, and time-to-market delays are only a few of them. Current verification methodologies heavily rely on the skills and experience of hardware engineers. This dependence further complicates the verification process. Large Language Models (LLMs) have already become an integral part of software engineering. They are being used for code and test generation, documentation, debugging, etc. Now, researchers actively explore how LLMs can be useful for the hardware domain as well. To contribute to this goal and to address the aforementioned problems, this work investigates how LLMs can advance hardware verification and introduces a mutation testing framework that uses an LLM as the mutation generator. The framework injects context-aware faults into microarchitecture designs. Then, verification infrastructures are evaluated based on their ability to detect these faults. Such an approach allows engineers to find weaknesses in test suites. The framework was assessed on the extensively verified, open-source RISC-V core CVA6. Hopefully, it brings a fresh perspective to the current verification methodologies.