Hierarchical Temporal Memory using Memristor Networks: A Survey
Loading...
Date
2018-09-24
Authors
Krestinskaya, Olga
Dolzhikova, Irina
James, Alex Pappachen
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers
Abstract
This paper presents a survey of the currently available
hardware designs for implementation of the human cortex
inspired algorithm, Hierarchical Temporal Memory (HTM). In
this review, we focus on the state of the art advances of
memristive HTM implementation and related HTM applications.
With the advent of edge computing, HTM can be a potential
algorithm to implement on-chip near sensor data processing.
The comparison of analog memristive circuit implementations
with the digital and mixed-signal solutions are provided. The
advantages of memristive HTM over digital implementations
against performance metrics such as processing speed, reduced
on-chip area and power dissipation are discussed. The limitations
and open problems concerning the memristive HTM, such as the
design scalability, sneak currents, leakage, parasitic effects, lack
of the analog learning circuits implementations and unreliability
of the memristive devices integrated with CMOS circuits are also
discussed.
Description
https://ieeexplore.ieee.org/document/8471012
Keywords
Hierarchical Temporal Memory, Spatial Pooler, Temporal Memory, Memristor, Spin-neuron, Crossbar
Citation
Krestinskaya, O., Dolzhikova, I., & James, A. P. (2018). Hierarchical Temporal Memory Using Memristor Networks: A Survey. IEEE Transactions on Emerging Topics in Computational Intelligence, 2(5), 380–395. https://doi.org/10.1109/tetci.2018.2838124