Feature extraction without learning in an analog Spatial Pooler memristive-CMOS circuit design of Hierarchical Temporal Memory [Article]
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Date
2018-03-14
Authors
Krestinskaya, Olga
James, Alex Pappachen
Journal Title
Journal ISSN
Volume Title
Publisher
Springer US
Abstract
Hierarchical temporal memory (HTM) is a neuromorphic algorithm that emulates sparsity, hierarchy and modularity resembling the working principles of neocortex. Feature encoding is an important step to create sparse binary patterns. This sparsity is introduced by the binary weights and random weight assignment in the initialization stage of the HTM. We propose the alternative deterministic method for the HTM initialization stage, which connects the HTM weights to the input data and preserves natural sparsity of the input information. Further, we introduce the hardware implementation of the deterministic approach and compare it to the traditional HTM and existing hardware implementation. We test the proposed approach on the face recognition problem and show that it outperforms the conventional HTM approach.
Description
https://arxiv.org/abs/1803.05131
Keywords
Article, Hierarchical Temporal Memory, Memristors, Spatial Pooler, Rule based approach, Analog circuits
Citation
Krestinskaya, O. & James, A.P. Analog Integr Circ Sig Process (2018) 95: 457. https://doi.org/10.1007/s10470-018-1161-1