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Hardware Implementation of Probabilistic Neural Network

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dc.contributor.author Akhmetov, Yerbol
dc.date.accessioned 2019-03-13T08:10:18Z
dc.date.available 2019-03-13T08:10:18Z
dc.date.issued 2018-12
dc.identifier.citation Akhmetov, Yerbol (2018). Hardware Implementation of Probabilistic Neural Network. Nazarbayev University School of Engineering en_US
dc.identifier.uri http://nur.nu.edu.kz/handle/123456789/3791
dc.description.abstract A physical implementation of a non-volatile resistive switching device (ReRAM) and linking its concept to memristor triggered prolific research in neuromorphic and memory related fields in 2008. This resistive switching device lately generalized as memristor has a property of changing the resistance depending on its present resistive state and applied bias and retaining the established resistive state for a long duration after removal of the bias. Due to its nanoscale size and memory properties, the memristive devices are widely employed in designing artificial neural networks using crossbar architectures. Among various neural networks, a probabilistic neural network stands out by its straightforward training process that facilitates crossbar-based hardware implementation, which is the primary objective of this work. This thesis first makes an overview on the probabilistic neural network and hardware implementations of it. Then, an analog circuit design of the probabilistic neural network is proposed, which consists of three main components: crossbar section, hidden layer block, and maximum selector circuits. To address the issue of the sneak path in crossbar architectures, a modular crossbar approach is employed. In this method, a large crossbar is separated into several sub-crossbars of smaller sizes. It is demonstrated that this technique significantly reduces the sneak path current which commonly deteriorates the performance of the crossbar systems. In order to perform subtraction and exponential operations of the PNN, CMOS-based subtraction and exponential circuits are adopted and modified to have lower area and power consumption. The performance of the circuit implementation of the PNN is tested using MNIST dataset and compared with the software version. The SPICE simulations using 45nm CMOS process technology revealed good correspondence between hardware and software realizations. The system level simulations demonstrated that the hardware realization of the PNN can have up to 93.3% recognition accuracy of the handwritten digits for properly selected smoothing parameter. en_US
dc.language.iso en en_US
dc.publisher Nazarbayev University School of Engineering and Digital Sciences en_US
dc.rights Attribution-NonCommercial-ShareAlike 3.0 United States *
dc.rights.uri http://creativecommons.org/licenses/by-nc-sa/3.0/us/ *
dc.title Hardware Implementation of Probabilistic Neural Network en_US
dc.type Master's thesis en_US
workflow.import.source science

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